1. Field of the Invention
The embodiments disclosed herein relate to a liquid crystal display and a method of driving the same.
2. Discussion of the Related Art
Active matrix type liquid crystal displays display a moving picture using a thin film transistor (TFT) as a switching element. The active matrix type liquid crystal displays have been implemented in televisions as well as display devices in portable devices, such as office equipment and computers, because of the thin profile of an active matrix type liquid crystal displays. Accordingly, cathode ray tubes (CRT) are being rapidly replaced by the active matrix type liquid crystal displays.
A liquid crystal display includes a plurality of source drive integrated circuits (ICs) supplying a data voltage to data lines of a liquid crystal display panel, a plurality of gate drive ICs sequentially supplying a gate pulse (i.e., a scan pulse) to gate lines of the liquid crystal display panel, and a timing controller controlling the source drive ICs and the gate drive ICs. In the liquid crystal display, digital video data is input to the timing controller through an interface. The timing controller supplies the digital video data, a clock for sampling the digital video data, a control signal for controlling an operation of the source drive ICs, and the like to the source drive ICs through an interface such as a mini low-voltage differential signaling (LVDS) interface. The source drive ICs deserializes the digital video data serially input from the timing controller to output parallel data and then converts the parallel data into an analog data voltage using a gamma compensation voltage to supply the analog data voltage to the data lines.
The timing controller supplies necessary signals to the source drive ICs using a multi-drop manner of commonly applying the clock and the digital video data to the source drive ICs. Because the source drive ICs are cascade-connected to one another, the source drive ICs sequentially sample the digital video data and then simultaneously output data voltages corresponding to 1 line. In such a data transfer method, many lines such as R, G, and B data transfer lines and clock transfer lines are necessary between the timing controller and the source drive ICs. Because the mini LVDS interface is a manner of transferring each of the digital video data and the clock in the form of a pair of differential signals, which are out of phase with each other, at least 14 data transfer lines between the timing controller and the source drive ICs are necessary to simultaneously transfer odd data and even data. Accordingly, because many data transfer lines have to be formed on a printed circuit board (PCB) positioned between the timing controller and the source drive ICs, it is difficult to reduce the number of data transfer lines.